A conventional LSI design method is typically represented by a flowchart as shown in FIG. 2. That is, RTL modeling and logic verification are performed first, and next logic synthesis, layout, and timing verification are performed to generate mask data. Then, a prototype is made and evaluated to ship samples. Problems detected in the verification and evaluation are corrected while being returned to the respective required steps. At present, high performance logic simulators and logic synthesis tools allow logic errors to be eliminated almost completely. However, as for a malfunction caused by timing variations due to parasitic resistance and capacitance generated after the layout, it is much more difficult to be eliminated as compared with errors caused only by logic structures. In general, timing verification is performed after the layout in view of parasitic resistance and capacitance, though multiple modifications of the layout are required, leading to a longer design period of time. In addition, there are errors that cannot be eliminated in the design step because of low accuracy of adjustment.